1. Field of the Invention
The present invention relates to a redundancy circuit and a semiconductor memory device using the same.
2. Description of the Related Art
Conventionally, in a semiconductor memory such as a RAM (random access memory) or a semiconductor integrated circuit with a memory circuit built therein, a redundancy circuit is provided to contains redundant memory columns or memory rows and a address setting circuit storing defective addresses, in order to relieve defective bits contained in a memory array and to improve a production yield.
Generally, it is carried out to set a defective address in the redundancy circuit by physically cutting a programmable fuse with laser. The redundant address stored through the cutting of the fuse as mentioned above is compared with an inputted address, and a memory row or column is replaced by a redundant memory row or column when both are coincident with each other.
FIG. 1 is a block diagram showing the structure of a semiconductor memory device containing a conventional redundancy circuit. Referring to FIG. 1, the semiconductor memory device has the redundancy circuit on the row side. However, the semiconductor memory device may have a redundancy circuit on the column side. The structure of the redundancy circuit on the column side is same as the redundancy circuit on the row side and it will be apparent to a person in the art.
Referring to FIG. 1, a redundancy circuit relating section mainly has a control logic circuit 115, a redundant cell check entry block 112, a decoder kill entry block 113, a redundancy control block 110, a row redundant cell array 125 and a data output buffer 128. The redundancy control block 110 has a redundancy decoder selecting circuit 102, a redundancy decoder 104, and a decoder killer circuit 106. The row redundant cell array 125 has a plurality of redundant cell rows.
The redundant cell check entry block 112 generates a redundant cell check entry signal 151 based on a control signal from the control logic circuit 115 and an inputted address, and supplies it to the redundancy decoder selecting circuit 102 and the redundancy decoder 104. The decoder kill entry block 113 generates a decoder kill entry signal 140 based on a control signal from the control logic circuit 115 and the inputted address, and supplies it to the data output buffer 128.
The redundancy decoder selecting circuit 102 and the redundancy decoder 104 in the redundancy control block 110 are connected by a common line and output a redundancy determination signal 143. The redundancy decoder selecting circuit 102 receives the address from a row address buffer & refresh counter 119 and a redundant cell check entry signal 151 from the entry block 112, and outputs the redundancy determination signal 143 together with the redundancy decoder 104. The redundancy decoder 104 receives the address from the row address buffer & refresh counter 119, the redundant cell check entry signal 151 from the entry block 112 and a control signal 145 from the control logic circuit 115, and generates the redundancy determination signal 143. The redundancy determination signal 143 generated by the redundancy decoder selecting circuit 102 and the redundancy decoder 104 is outputted to the decoder killer circuit 126 and the row redundant cell array 125. Thus, the row redundant cell array 125 specifies one of the plurality of redundant cell rows based on the redundancy determination signal 143. The decoder killer circuit 106 in the redundancy control block 110 generates a decoder killer signal 144 from the redundancy determination signal 143 to indicate whether or not the redundant cell array 125 is used. The decoder killer signal 144 is supplied to the data output buffer 128 and the row decoder 124. The row decoder 124 stops the operation in response to decoding killer signal. Also, the data output buffer 128 outputs the decoder killer signal 144 or a memory cell data to an external unit through an I/O terminal in response to the decoder kill entry signal 140.
FIG. 2 is a block diagram showing the detailed structure of the redundancy control block 110 shown in FIG. 1. In this example, it is supposed that it is possible to select which of the four redundant cell rows in the row redundant cell array 125. Referring to FIG. 2, the redundancy decoder selecting circuit 102 has address setting circuit 102-0 and four selecting circuits 102-1 to 102-4 with a same circuit structure. Also, the redundancy decoder 104 has the address setting circuit 104-0 and fuse circuits 104-1 to 104-4. The selecting circuits 102-1 to 102-4 and the fuse circuits 104-1 to 104-4 are connected by corresponding redundancy determination signal lines 143 (143-1, 143-2, 143-3, 143-4: not shown).
The fuse circuit 104-1 has a P-channel transistor having a source connected with a power supply potential Vcc. A precharge signal 145 is supplied from the control logic circuit 115 to the gate of the P-channel transistor. The drain of P-channel transistor is connected with the redundancy determination signal 143-1. Also, the fuse circuit 104-1 has a fuse section to each of a True side and a Not side of each of address bits A0 to Aj. The fuse section contains an N-channel transistor and a fuse. The drain of the N-channel transistor is connected with the redundancy determination signal 143-1 and the source is connected with the one end of the fuse. The other end of the fuse is grounded. A corresponding True address bit or Not address bit is supplied to the gate of each N-channel transistor.
Also, each of the fuse circuits 104-2, 104-3, 104-4 has a same circuit structure as the fuse circuit 104-1. The fuse of each fuse section in the fuse circuits 104 (104-1, 104-2, 104-3 and 104-4) is previously cut and programmed with laser in accordance with an address used for a redundancy operation.
The address setting circuit 104-0 contains NOR circuits 165-1 and 165-2 and an inverter 165-3 to the address bit A0. One of the input terminals of the NOR circuit 165-1 is connected with the redundant cell check entry signal 151, and the other input terminal of the NOR circuit 165-1 is connected with the address bit A0. The inverter 165-3 inverts the address bit A0. One of the input terminals of the NOR circuit 165-2 is connected with the redundant cell check entry signal 151, and the other input terminal of the NOR circuit 165-2 is connected with an inverted address bit A0. The address setting circuit 104-0 has the same circuits as the circuit for the address bit A0 for each of the address bits A1 to Aj. Each of the outputs of the NOR circuits of the address setting circuit 104-0 is supplied to the gate of the N-channel transistor on the True side or the Not side corresponding to the address bit of each of the fuse circuits.
The selecting circuit 102-1 has two N-channel transistors. The drain of each of the N-channel transistors is connected with the redundancy determination signal 143-1 as the common signal. The source of each of the N-channel transistors is grounded. Each of the selecting circuits 102-2, 102-3 and 102-4 has the same circuit structure as the selecting circuit 102-1.
The address setting circuit 102-0 has an inverter 160, NOR circuits 161-1 and 161-2 and an inverter 161-3 to an address bit RA0, and the NOR circuits 162-1 and 162-2 and an inverter 162-3 to an address bit RA1. The inverter 160 inverses the redundant cell check entry signal 151. One of the input terminals of the NOR circuit 161-1 is connected with the inverted redundant cell check entry signal 151, and the other input terminal of the NOR circuit 161-1 is connected with the address bit RA0. The inverter 161-3 inverts the address bit A0. One of the input terminals of the NOR circuit 161-2 is connected with the inverted redundant cell check entry signal 151, and the other input terminal of the NOR circuit 161-2 is connected with the inverted address bit RA0. The address setting circuit 102-0 has the same circuit structure as the circuit structure for the address bit RA0 for the address bit RA1. The output of the NOR circuit 161-1 of the address setting circuit 102-0 is supplied to the gate of one of the N-channel transistors in the selecting circuits 102-1 and 102-2. The output of the NOR circuit 161-2 is supplied to the gate of one of the N-channel transistors of the selecting circuits 102-3 and 102-4. The output of the NOR circuit 162-1 is supplied to the gate of the other N-channel transistor of the selecting circuits 102-1 and 102-3. The output of the NOR circuit 162-2 is supplied to the gate of the other N-channel transistor of the selecting circuits 102-2 and 102-4.
The decoder killer circuit 106 has an NOR circuit which inputs the redundancy determination signals 143-1, 143-2, 143-3, 143-4 and generates the decoder killer signal 144.
The address bits RA0 and RA1 supplied to the redundant selection decoder 102 are different from the address bits A0 to Aj supplied to the redundancy decoder 104. The address bits RA0 and RA1 may be supplied from external terminals or may be generated inside.
The redundancy circuit has three operation modes, i.e., (1) a normal mode, (2) a redundant cell check test mode, and (3) a roll call test mode. In (1) the normal mode, one redundant cell row of the row redundant cell array 125 is accessed which row is specified based on the address from the row address buffer 119. In (2) the redundant cell check test mode, whether or not the row redundant cell array is normal is tested. Lastly, in (3) the roll call test mode, whether or not the row redundant cell array 125 is used is tested. It should be noted that the fuse of each fuse circuit of the redundancy decoder 104 is previously cut in accordance with the address of the redundant memory cell of the memory cell array 125.
The above three operation modes will be described. In either of the three operation modes, the precharge signal 145 of an L level is first supplied from the control logic circuit 115 to the redundancy decoder 104 as a control signal. The P-channel transistors of the fuse circuits 104-1, 104-2, 104-3, and 104-4 are turned on. Thus, the redundancy determination signals 143-1, 143-2, 143-3 and 143-4 corresponding to the fuse circuits 104-1, 104-2, 104-3, and 104-4 are set to the power supply voltage Vcc (H level).
In (1) the normal mode, the redundant cell check entry block 112 generates the redundant cell check entry signal 151 of the L level based on the control signal from the control logic circuit 115 and the inputted address. Also, the decoder kill entry block 113 outputs the decoder kill entry signal 140 of the L level based on the control signal from the control logic circuit 115 and the inputted address. In case of the redundant cell check entry signal 151 of the L level, the outputs of the NOR circuits 161-1, 161-2, 162-1, and 162-2 always becomes the L level because the output of the inverter 160 of the address setting circuit 102-0 becomes the H level. As a result, all the N-channel transistors of the selecting circuits 102-1, 102-2, 102-3, and 102-4 become an OFF state and the redundancy decoder selecting circuit 102 is set to the disable state. Therefore, the selecting circuits 102-1, 102-2, 102-3, and 102-4 do not have an influence on the redundancy determination signal 143.
In the address setting circuit 104-0 of the redundancy decoder 104, all the NOR circuits are active because the redundant cell check entry signal 151 is in the L level and the output of each NOR circuit changes in accordance with the address bits A0 to Aj supplied from the row address buffer 119.
The fuses corresponding to the supplied address bits A0 to Aj are generally cut. However, in case that all the fuses are not yet cut, all the redundancy determination signals 143-1, 143-2, 143-3, and 143-4 corresponding to the fuse circuits 104-1, 104-2, 104-3, and 104-4 become the L level. The redundancy determination signals 143 (143-1, 143-2, 143-3, and 143-4) are outputted to the row redundant cell array 125 and the decoder killer circuit 106. The row redundant cell array 125 ignores all the redundancy determination signals of the L level. The decoder killer circuit 106 generates the decoder killer signal 144 of the H level based on the redundancy determination signals 143 of the L level and outputs it to the row decoder 124 and the data output buffer 128. At this time, because the decoder kill entry signal 140 of the L level is outputted from the decoder kill entry block 113, the decoder killer signal 144 is never outputted from the data output buffer 128. Also, when the decoder killer signal 144 is in the H level, the row decoder 124 operates normally. Thus, the read/write operation is carried out through a sense amplifier 123, a data control logic circuit 121, a latch circuit 127, a data output buffer 128, and a data input buffer 129, using a memory cell array 126.
On the other hand, when either of the redundancy determination signals 143-1, 143-2, 143-3, and 143-4 corresponding to the fuse circuits 104-1, 104-2, 104-3, and 104-4 becomes the H level based on the address bits A0 to Aj, the decoder killer circuit 106 generates and outputs the decoder killer signal 144 of the L level to the row decoder 124 and to the data output buffer 128. At this time, because the decoder kill entry signal 140 of the L level is outputted from the decoder kill entry block 113, the decoder killer signal 44 is never outputted from the data output buffer 128. Also, the row decoder 124 is set to the disable state in response to the decoder killer signal 144 of the L level and stops the operation. Therefore, the memory cell array 126 is never used. Also, the redundancy determination signals 143-1, 143-2, 143-3, and 143-4 are supplied to the row redundant cell array 125 and one redundant cell row in the row redundant cell array 125 is selected. The read/write operation is carried out to the selected redundant cell row through the sense amplifier 123, the data control logic circuit 121, the latch circuit 127, the data output buffer 128, and the data input buffer 129.
Next, the operation of (2) the redundant cell check test mode will be described. In (2) the redundant cell check test mode, a test mode entry block 112 outputs the redundant cell check entry signal 151 of the H level based on the control signal from the control logic circuit 115 and the inputted address. Also, the decoder kill entry block 113 outputs the decoder kill entry signal 140 of the L level based on the control signal from the control logic circuit 115 and the inputted address. Because the redundant cell check entry signal 151 is in the H level, the outputs of all the NOR circuits become the L level in the address setting circuit 104-0 of the redundancy decoder 104. Therefore, all the N-channel transistors in the fuse circuits 4-1, 4-2, 4-3, 4-4 become the OFF state and the redundancy decoder 104 does not have an influence on the redundancy determination signal 143.
On the other hand, the output of the inverter 160 of the address setting circuit 102-0 of the redundancy decoder selecting circuit 102 is set to the L level, and the outputs of the NOR circuits 161-1, 161-2, 162-1 and 162-2 of the address setting circuit 102-0 are determined based on the address bits RA0 and RA1. As the result, one of the redundancy determination signals 143-1, 143-2, 143-3 and 143-4 of the selecting circuits 102-1, 102-2, 102-3, and 102-4 is set to the H level, and all the other ones become the L level based on the address bits RA0 and RA1.
The redundancy determination signals 143 (143-1, 143-2, 143-3, and 143-4) are outputted to the row redundant cell array 125 and the decoder killer circuit 106. Because either of the redundancy determination signals 143 is in the H level, the decoder killer circuit 106 generates the decoder killer signal 144 of the L level and outputs to the row decoder 124 and to the data output buffer 128. At this time, because the decoder kill entry signal 140 of the L level is outputted from the decoder kill entry block 113, the decoder killer signal 144 is never outputted from the data output buffer 128. Also, when the decoder killer signal 144 is in the L level, the row decoder 124 is set to the disable state in response to the decoder killer signal 144 of the L level and stops the operation. Therefore, the memory cell array 126 is never used. Also, the redundancy determination signals 143 are supplied to the row redundant cell array 125, and the redundant cell row of the row redundant cell array 125 corresponding to the redundancy determination signal 143 of the H level is selected. The read/write operation is carried out through the sense amplifier 123, the data control logic circuit 121, the latch circuit 127, the data output buffer 128, and the data input buffer 129 to the selected redundant cell row.
At this time, if the address bits RA0 and RA1 supplied from the row address buffer 119 are changed, the data can be read in order from the redundant cell row of the row redundant cell array 125 and the state of the redundant cell row can be checked.
Next, the operation of (3) the roll call test mode will be described. In (3) the roll call test mode, the redundant cell check entry block 112 outputs the redundant cell check entry signal 151 of the L level based on the control signal from the control logic circuit 115 and the inputted address. Also, the decoder kill entry block 113 outputs the decoder kill entry signal 140 of the H level to the data output buffer 128 based on the control signal from the control logic circuit 115 and the inputted address. Therefore, the output of the inverter 160 of the address setting circuit 102-0 of the redundancy decoder selecting circuit 102 becomes the H level, all the NOR circuits 161-1 of the address setting circuit 102-0, 161-2, 162-1 and 162-2 output the L level. As the result, all the N-channel transistors of the selecting circuits 102-1, 102-2, 102-3, and 102-4 become the OFF state and the redundancy decoder selecting circuit 102 is set to the disable state. Therefore, the selecting circuits 102-1, 102-2, 102-3, and 102-4 do not have an influence on the redundancy determination signal 143 and also the redundancy decoder selecting circuit 102 does not have an influence on the selection of the fuse circuit.
On the other hand, at the address setting circuit 104-0 of the redundancy decoder 104, all the NOR circuits are active and the output of the NOR circuit changes in accordance with the address bits A0 to Aj supplied from the row address buffer 119.
When the fuse circuit in which a fuse is cut in correspondence to the inputted address bits A0 to Aj exists, either of the redundancy determination signals 143-1, 143-2, 143-3, and 143-4 of the fuse circuits 104-1, 104-2, 104-3, and 104-4 is set to the H level based on the address bits A0 to Aj. In this case, the redundancy determination signals 143-1, 143-2, 143-3, and 143-4 are outputted to the decoder killer circuit 106 and the row redundant cell array 125. The decoder killer circuit 106 generates and outputs the decoder killer signal 144 of the L level to the row decoder 124 and the data output buffer 128. At this time, because the decoder kill entry signal 140 of the H level is outputted from the decoder kill entry block 113, the decoder killer signal 144 is outputted from the data output buffer 128. Also, the row decoder 124 is set to the disable state in response to the decoder killer signal 144 of the L level and stops the operation. Therefore, the memory cell array 126 is never used. Also, the redundancy determination signals 143-1, 143-2, 143-3, and 143-4 are supplied to the row redundant cell array 125 and the redundant cell row corresponding to the H level of the row redundant cell array 125 is selected. Because the decoder kill entry signal 140 is in the H level even if data is supposed to have been read through the sense amplifier 123, the data control logic circuit 121, and the latch circuit 127 from the selected redundant cell row, data from the redundant cell row is never outputted from the data output buffer 128.
By the way, it is demanded to individually test whether or not the fuses are in the programmed state and whether or not a fuse of a specific fuse section of a specific fuse circuit of the redundancy decoder 104 is cut. However, it is conventionally impossible to check whether one optional fuse is cut and whether or not the fuse is in the programmed state.
In conjunction with the above description, technique disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 3-22298) will be described with reference to FIG. 3. In this conventional example, the detecting circuit is described only which carries out the roll call test operation simply.
A redundancy decoder is composed of EX-OR (XOR) circuits 514A0 to 514An which carry out an exclusive OR operation of address bits A0 to An and the outputs of fuse determining circuits 503A0 to 503An and an AND circuit 504c which inputs those outputs.
A redundant address is set by cutting fuses of fuse determining circuits 503A0 to 503An. The level of each of output signals FA0 to FAn of the fuse determining circuits 503A0 to 503An is in the H level when a corresponding fuse is cut, and the level of each of the output signals FA0 to FAn is in the L level when the corresponding fuse is not cut. Thus, the conductive states (the L level)/conductive state (the H level) states of the fuses of the fuse determining circuits 503A0 to 503An, and an address signal are compared and the comparing result is outputted from the XOR circuits 514A0 to 514An.
In order to confirm the operation of the redundancy decoder, it is supposed that there are four address bits A0 to A3 now and the fuses of the fuse determining circuits 3A0 to 3An are programmed in the states of ON, OFF, OFF and ON in order from the side of the address bit A0. Thus, the output signals FA0 to FA3 of the fuse determining circuits 503A0 to 503An becomes “0110”. At this time, if the address bits A0 to A3 of “0110” are supplied, the outputs of the respective XOR circuits 514A0 to 514An are set to the H level, and the output of the AND circuit 504c is set to the H level. Thus, a redundant cell row is selected. If the address bits A0 to A3 with the other value is supplied, the output of either of the XOR 14A0 to 14An is set to the L level, and the redundant cell row is never selected. Thus, it can be confirmed that the redundant cell operates right.
In accordance with this conventional example, in order to check the fuse state corresponding to the address bit A0, an address of “1000” with the address bit A0 of the H level and the address bits A0 to A3 of the L level is supplied. In order to check the fuse state corresponding to the address bit A1, an address of “0100” with the address bit A1 of the H level and the address bits A0, A2 and A3 of the L level is supplied.
As described above, it is supposed that the fuses are programmed in the state of ON, OFF, OFF and ON in order from the address bit A0. At this time, when the address of “1000” is supplied to check the fuse corresponding to the address bit A0, the outputs of the XOR circuits 514A0 to 514An are set to “1110”, and the output of an OR circuit 504d of the fuse detecting circuit is set to the H level. Next, when the address of “0100” is supplied to check the fuse corresponding to the address bit A1, the outputs of the XOR circuits 514A0 to 514An are set to “0010” and the output of the OR circuit 504d of the fuse detecting circuit is set to the H level.
In this example, the fuse corresponding to the address bit A0 is programmed to the ON state, the fuse corresponding to the address bit A1 is programmed to the OFF state. Although the states of the fuses are different, the output of the OR circuit 4d is set to the H level. From this fact, it could be understood that the state of each fuse cannot be checked.
The output of the AND circuit 504c of a defective address detecting circuit 504 is set to the H level only when the address bits A0 to An are supplied such that all the outputs of the XOR circuits 514A0 to 514An are set to the H level. Also, the output of the OR circuit 504d is set to the L level only when the address bits A0 to An are supplied such that all the outputs of the XOR circuits 514A0 to 514An are set to the L level.
This conventional technique cannot check each state of the fuse, whether the fuse is cut or not when a plurality of redundancy decoders exists. Also, when a fuse is erroneously programmed to the state that a redundancy decoder is not selected, the error cannot be detected. In the same way, when fuses are erroneously programmed to the state that redundancy decoders are selected, the error cannot be detected.
In conjunction with the above description, a semiconductor memory device is disclosed in Japanese Laid Open Patent application (JP-A-Heisei 4-205897). In this conventional example, the semiconductor memory device is composed of a main memory, a redundant memory, a route to transfer a signal from an input terminal to an internal circuit, and a sense circuit connected with the input terminal. A fuse and a transfer gate are provided for the end portion of the sense circuit. An end of the fuse is connected with a higher voltage or a ground voltage, and the fuse is cut based on an address for the redundant memory. The transfer gate is set to a conductive state or a non-conductive state in response to a control signal. The address for the redundant memory is sensed based on leakage current from the input terminal.
Also, a redundancy circuit using anti-fuse is disclosed in Japanese Laid Open Patent application (JP-P2002-133895A). In this conventional example, the redundancy circuit includes first and second electrical fuses whose characteristics are changed when a voltage higher than a predetermined level is applied. A differential amplifier receives two signal voltages depending on a difference between the first and second electrical fuses in characteristic, and amplifies the two signal voltages. A storage circuit stores the amplified signal voltages. A switch circuit connects the storage circuit with the differential amplifier and disconnects the storage circuit from the differential amplifier.